The present invention relates to photolithography, and in particular relates to optical proximity correction methods utilizing serifs, which are variable in size and position, based on the location of the particular serif relative to the surrounding features.
In addition, the present invention relates to a device manufacturing method using a lithographic apparatus comprising:
a radiation system for providing a projection beam of radiation;
a mask table for holding a mask, serving to pattern the projection beam;
a substrate table for holding a substrate;
a projection system for projecting the patterned projection beam onto a target portion of the substrate.
Lithographic projection apparatus (tools) can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask contains a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatusxe2x80x94commonly referred to as a step-and-scan apparatusxe2x80x94each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the xe2x80x9cscanningxe2x80x9d direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction; since, in general, the projection system will have a magnification factor M (generally  less than 1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic apparatus as here described can be gleaned, for example, from U.S. Pat No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g. an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes can be obtained, for example, from the book xe2x80x9cMicrochip Fabrication: A Practical Guide to Semiconductor Processingxe2x80x9d, Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997, ISBN 0-07-067250-4, incorporated herein by reference.
The lithographic tool may be of a type having two or more substrate tables (and/or two or more mask tables). In such xe2x80x9cmultiple stagexe2x80x9d devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic tools are described, for example, in U.S. Pat. No. 5,969,441 and WO 98/40791, incorporated herein by reference.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way.
These design rule limitations are typically referred to as xe2x80x9ccritical dimensionsxe2x80x9d (CD). A critical dimension of a circuit can be defined as the smallest width of a line or the smallest space between two lines. Thus, the CD determines the overall size and density of the designed circuit.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask). Another goal is to use as much of the semiconductor wafer real estate as possible. As the size of an integrated circuit is reduced and its density increases, however, the CD of its corresponding mask pattern approaches the resolution limit of the optical exposure tool. The resolution for an exposure tool is defined as the minimum feature that the exposure tool can repeatedly expose on the wafer. The resolution value of present exposure equipment often constrains the CD for many advanced IC circuit designs.
As the critical dimensions of the circuit layout become smaller and approach the resolution value of the exposure tool, the correspondence between the mask pattern and the actual circuit pattern developed on the photoresist layer can be significantly reduced. The degree and amount of differences in the mask and actual circuit patterns depends on the proximity of the circuit features to one another.
Accordingly, pattern transference problems are referred to as xe2x80x9cproximity effects.xe2x80x9d Proximity effects occur when very closely spaced circuit pattern features are lithographically transferred to a resist layer on a wafer. The light waves of the closely spaced circuit features interact, thereby distorting the final transferred pattern features.
Another common proximity effect problem caused by approaching the resolution limit of the exposure tool is that the corners of the photoresist (both concave and convex) tend to overexpose or underexpose due to a concentration or lack of energy at each of the corners. For example, during exposure to light or radiation the photoresist layer integrates energy contributions from all surrounding areas. Thus, the exposure dose in one vicinity of the wafer is affected by the exposure dose in neighboring vicinities.
Because a corner region in a mask pattern lacks neighboring regions, the exposure dose to a corner of the photoresist layer will always be less than the exposure dose to the main body of the layer. The corners of the developed photoresist pattern, therefore, tend to be rounded, rather than angular, due to the fact that less energy has been delivered to the corners than to the other areas of the masked pattern. In small, dense integrated circuits, such as VLSI circuits, these rounding effects can cause a significant degradation to the circuit""s performance. Moreover, rounding results in a loss of contact surface area, which correspondingly reduces the total area available for conduction and accordingly results in an undesirable increase in contact resistance.
To help overcome the significant problem of proximity effects, a number of techniques are used to add sub-lithographic features to mask patterns. Sub-lithographic features have dimensions less than the resolution of the exposure tool, and therefore do not transfer to the photoresist layer. Instead, sub-lithographic features interact with the original mask pattern and compensate for proximity effects, thereby improving the final transferred circuit pattern.
Examples of such sub-lithographic features are scattering bars and anti-scattering bars, such as disclosed in U.S. Pat. No. 5,821,014 (incorporated herein by reference), which are added to mask patterns to reduce differences between features within a mask pattern caused by proximity effects. Another technique used to improve circuit pattern transference from design to wafer is to add features to the mask pattern called xe2x80x9cserifsxe2x80x9d, such as disclosed in U.S. Pat. No. 5,707,765 (incorporated herein by reference). Serifs are typically sub-lithographic square-shaped features positioned on each corner of a circuit feature. The serifs serve to xe2x80x9csharpenxe2x80x9d the corners in the final transferred design on the wafer, thereby improving the correspondence between the actual circuit design and the final transferred circuit pattern on the photoresist layer. Serifs are also used at the intersection areas of differing circuit patterns in order to compensate for the distortion factor caused by the intersection of two different circuit patterns.
In particular, it is known to include xe2x80x9cpositivexe2x80x9d serifs at convex vertices so as to adjust the exposure energy of the mask at the vertex to prevent loss of the corner, and to include xe2x80x9cnegativexe2x80x9d serifs at concave vertices. The xe2x80x9cnegativexe2x80x9d serifs essentially remove a portion of the mask pattern at the concave vertex so as to attempt to maintain an accurate representation of the concave vertex in the final pattern formed on the wafer.
However, prior to the present invention, known methods of applying serifs to feature patterns utilized serifs having a predetermined, non-adjustable size. For example, each positive serif contained in the mask pattern had the same dimension, and similarly, each negative serif contained in the mask pattern had the same dimension. Furthermore, in such known systems, the determination of whether or not a serif would be provided in a specific location was determined based solely on the distance of the serif to the next closest serif. In other words, if there was sufficient room to accommodate the predetermined, singular size serif without causing interference (i.e. bridging) with the closest adjacent serif, the serif would be included in the mask design. However, if inclusion of the serif would result in interference with another serif, both serifs were simply cancelled from the pattern, resulting in an undesirable degradation in the final mask pattern and subsequent feature printing.
Such known methods typically defined a minimum allowable distance between a serif and the adjacent serif. As stated, if two serifs were separated by less than the minimum allowable distance, the serifs simply cancelled one another (i.e. both serifs were omitted).
While such known methods of placing serifs are acceptable when the minimum distance between features is sufficiently large, as today""s photolithography techniques are continually reducing the minimum distance required between features, the foregoing known method can result in an unacceptable elimination of a significant number of serifs, which correspondingly results in an undesirable reduction in the accuracy of the reproduction of the desired circuit on the wafer.
For example, in the case of a line end having two convex vertices, it is necessary to place positive serifs on each vertex so as to prevent undesirable shortening of the line formed on the wafer. However, due to ever decreasing line widths, in the foregoing serif placement method, the serifs on the two vertices would simply cancel each other because the serifs would be too close to one another. As stated, this results in an undesirable line shortening in the final pattern.
In addition, known serif placement methods do not provide a mechanism for determining whether or not a serif would result in interference with an adjacent feature. This is due to the fact that the CD for typical circuits would readily allow for placement of the serif without any resulting interference. However, as the CD of circuit designs is continually decreasing, it is increasingly likely that positive serifs may interfere with adjacent features.
Accordingly, there exists a need for a method of performing optical proximity correction utilizing serifs that allows for the flexible design of serifs, such that serifs located proximate one another that fail to satisfy a minimum distance requirement are not simply cancelled from the mask pattern. In addition, there is a need for an optical proximity correction method that verifies and prevents interference between serifs and adjacent features.
In an effort to solve the aforementioned needs, it is an object of the present invention to provide an optical proximity correction method utilizing serifs that allows for the modification of the dimension of each serif, as well as the position of each serif, on an individual basis so as to allow adjacent serifs that initially fail to satisfy a minimum distance requirement to be modified in size and/or position so as to meet the minimum distance requirement.
It is also an object of the present invention to provide an optical proximity correction method that verifies and prevents interference between serifs and adjacent features.
More specifically, in a first embodiment, the present invention relates to a method of forming a mask for transferring a lithographic pattern onto a substrate by use of a lithographic exposure apparatus (tool), where the pattern comprises a plurality of features each of which has corresponding edges and vertices. The method comprises the steps of forming serifs on a plurality of the vertices contained in the lithographic pattern, where each of the serifs has a (substantially) rectangular shape, and determining the size of each serif independently on the basis of the lengths of the feature edges forming a given vertex, and the xe2x80x9chorizontalxe2x80x9d and xe2x80x9cverticalxe2x80x9d distance of the given vertex to the nearest feature edge, wherein the position of each side of a given serif is independently adjustable relative to the position of the remaining sides of the given serif. As here employed, the terms xe2x80x9chorizontalxe2x80x9d and xe2x80x9cverticalxe2x80x9d refer to mutually orthogonal directions that lie within the plane of the mask pattern; conventionally, they correspond to the X and Y axes parallel to which the edges of most (if not all) of the mask features extend.
In a second embodiment, the present invention relates to a method of forming a mask for transferring a lithographic pattern onto a substrate by use of a lithographic exposure apparatus, where the pattern comprises a plurality of features each of which has corresponding edges and vertices. The method comprises the steps of forming a serif on at least one of the vertices contained in the lithographic pattern, and determining the size of the serif on the basis of at least the length of the feature edges forming said one of the vertices, where the length of each of the feature edges is determined by measuring the distance from said one of the vertices to the closest feature edge that exceeds either a predefined jog tolerance or a predefined slope tolerance.
In a third embodiment, the present invention relates to a method of forming a mask for transferring a lithographic pattern onto a substrate by use of a lithographic exposure apparatus, where the pattern comprises a plurality of line end features, each of which has two vertices and a feature edge. The method comprises the steps of forming a serif on each of the vertices contained in a given line end feature, determining the length of the feature edge, and adjusting the size of each serif formed on the vertices of the given line end feature such that the serifs contact each other so as to form one contiguous surface when the length of the feature edge is less than a predetermined size.
As described in further detail below, the present invention provides significant advantages over the prior art. Most importantly, the optical proximity method of the present invention provides for individual and flexible control of each serif so as to allow the size and position of each serif to be adjustable. As such, it is possible to modify the dimensions of serifs during the mask design process so that serifs that would otherwise be eliminated from the design satisfy minimum distance requirements. As a result, the present invention minimizes the elimination of serifs from the mask design, and the corresponding degradation in the pattern formed on the wafer.
Although specific reference may be made in this text to the use of the invention in the manufacture of ICs, it should be explicitly understood that the invention has many other possible applications. For example, it may be employed in the manufacture of integrated optical systems, guidance and detection patterns for magnetic domain memories, liquid-crystal display panels, thin-film magnetic heads, etc. The skilled artisan will appreciate that, in the context of such alternative applications, any use of the terms xe2x80x9creticlexe2x80x9d, xe2x80x9cwaferxe2x80x9d or xe2x80x9cdiexe2x80x9d in this text should be considered as being replaced by the more general terms xe2x80x9cmaskxe2x80x9d, xe2x80x9csubstratexe2x80x9d and xe2x80x9ctarget portionxe2x80x9d, respectively.
In the present document, the terms xe2x80x9cradiationxe2x80x9d and xe2x80x9cbeamxe2x80x9d are used to encompass all types of electromagnetic radiation, including ultraviolet radiation (e.g. with a wavelength of 365, 248, 193, 157 or 126 nm) and EUV (extreme ultra-violet radiation, e.g. having a wavelength in the range 5-20 nm).
The term mask as employed in this text may be broadly interpreted as referring to generic patterning means that can be used to endow an incoming radiation beam with a patterned cross-section, corresponding to a pattern that is to be created in a target portion of the substrate; the term xe2x80x9clight valvexe2x80x9d can also be used in this context. Besides the classic mask (transmissive or reflective; binary, phase-shifting, hybrid, etc.), examples of other such patterning means include:
A programmable mirror array. An example of such a device is a matrix-addressable surface having a viscoelastic control layer and a reflective surface. The basic principle behind such an apparatus is that (for example) addressed areas of the reflective surface reflect incident light as diffracted light, whereas unaddressed areas reflect incident light as undiffracted light. Using an appropriate filter, the said undiffracted light can be filtered out of the reflected beam, leaving only the diffracted light behind; in this manner, the beam becomes patterned according to the addressing pattern of the matrix-adressable surface. The required matrix addressing can be performed using suitable electronic means. More information on such mirror arrays can be gleaned, for example, from U.S. Pat. Nos. 5,296,891 and 5,523,193, which are incorporated herein by reference.
A programmable LCD array. An example of such a construction is given in U.S. Pat. No. 5,229,872, which is incorporated herein by reference.
Additional advantages of the present invention will become apparent to those skilled in the art from the following detailed description of exemplary embodiments of the present invention.
The invention itself, together with further objects and advantages, can be better understood by reference to the following detailed description and the accompanying schematic drawings.